7 things you must know about high-speed circuit layout

7 things you must know about high-speed circuit layout

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  • Time of issue:2021-07-07
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(Summary description)Many times the current required by digital circuits is discontinuous, so inrush current will be generated for some high-speed devices.

7 things you must know about high-speed circuit layout

(Summary description)Many times the current required by digital circuits is discontinuous, so inrush current will be generated for some high-speed devices.

  • Categories:Corporate News
  • Author:
  • Origin:
  • Time of issue:2021-07-07
  • Views:0

Power layout related

Many times the current required by digital circuits is discontinuous, so inrush current will be generated for some high-speed devices.

If the power trace is very long, the presence of inrush current will cause high-frequency noise, and this high-frequency noise will be introduced into other signals. In high-speed circuits, there will inevitably be parasitic inductance, parasitic resistance and parasitic capacitance, so the high-frequency noise will eventually be coupled to other circuits, and the presence of parasitic inductance will also lead to the ability of the trace to withstand the maximum surge current Decrease, which in turn leads to a partial voltage drop, which may disable the circuit.

So it is very important to add a bypass capacitor in front of the digital device. The larger the capacitance, the transmission energy is limited by the transmission rate, so a large capacitance and a small capacitance are generally combined to meet the full frequency range.

Avoid hot spots: signal vias will generate voids on the power layer and bottom layer. Therefore, unreasonable placement of vias is likely to increase the current density in certain areas of the power supply or ground plane. These areas where the current density increases are called hot spots.

Therefore, we must try our best to avoid this situation when setting the vias, so as to avoid the plane from being split, which will eventually lead to EMC problems.

Usually the best way to avoid hot spots is to place vias in a mesh pattern, so that the current density is uniform, and the planes will not be isolated at the same time, the return path will not be too long, and EMC problems will not occur.

Bending way of routing

When laying out high-speed signal lines, avoid bending the signal lines as much as possible. If you have to bend the trace, do not trace it at an acute or right angle, but rather use an obtuse angle.

When laying high-speed signal lines, we often use serpentine lines to achieve equal length. The same serpentine line is actually a kind of bend. The line width, spacing, and bending method should all be selected reasonably, and the spacing should meet the 4W/1.5W rule.

signal proximity

If the distance between high-speed signal lines is too close, it is easy to produce crosstalk. Sometimes, due to layout, board frame size and other reasons, the distance between our high-speed signal lines exceeds our minimum required distance, then we can only increase the distance between the high-speed signal lines as much as possible near the bottleneck. distance.

In fact, if the space is enough, try to increase the distance between the two high-speed signal lines.

routing stubs

The long stub line is equivalent to an antenna, and improper handling can cause serious EMC problems.

At the same time, the stub line will also cause reflections, reducing the integrity of the signal. Usually when a pull-up or pull-down resistor is added to a high-speed signal line, the stub line is most likely to be generated, and the wiring of the stub line can be daisy-lined.

According to experience, if the length of the stub line is greater than 1/10 of the wavelength, it can be used as an antenna, which will become a problem at this time.

Impedance is not continuous

The impedance value of a trace generally depends on its line width and the distance between the trace and the reference plane. The wider the trace, the lower its impedance. In some interface terminals and device pads, the principle is also applicable.

When the pad of an interface terminal is connected to a high-speed signal line, if the pad is particularly large at this time, and the high-speed signal line is particularly narrow, the impedance of the large pad is small, and the narrow trace must have large impedance. In this case, impedance discontinuity will occur, and signal reflection will occur if impedance is discontinuous.

So generally in order to solve this problem, a forbidden copper sheet is placed under the large pad of the interface terminal or device, and the reference plane of the pad is placed on another layer to increase the impedance and make the impedance continuous.

Via is another source of impedance discontinuity. In order to minimize this effect, the unnecessary copper skin connected to the inner layer and the via should be removed.

And this kind of operation can actually be eliminated by CAD tools during design or contact the PCB processing manufacturer to eliminate unnecessary copper and ensure the continuity of impedance.

Differential signal

High-speed differential signal lines, we must ensure equal width and equal spacing to achieve a specific differential impedance value. Therefore, try to ensure symmetry when routing differential signal lines.

It is forbidden to arrange vias or components in the differential pair. If vias or components are placed in the differential pair, EMC problems will occur and impedance discontinuities will also be caused.

Sometimes, some high-speed differential signal lines need to be connected in series with coupling capacitors. The coupling capacitor also needs to be arranged symmetrically, and the package of the coupling capacitor should not be too large. It is recommended to use 0402, 0603 is also acceptable, and capacitors above 0805 or side-by-side capacitors are best not to be used.

Usually, vias will produce huge impedance discontinuities, so for high-speed differential signal line pairs, minimize vias, and symmetrically arrange vias if they are to be used.

equal length

In some high-speed signal interfaces, generally, such as a bus, it is necessary to consider the arrival time and time lag error between the signal lines. For example, in a group of high-speed parallel buses, the arrival time of all data signal lines must be guaranteed to be within a certain time lag error to ensure the consistency of the setup time and the hold time. In order to meet this demand, we must consider equal lengths.

The high-speed differential signal line must ensure a strict time lag for the two signal lines, otherwise the communication is likely to fail. Therefore, in order to meet this requirement, a serpentine line can be used to achieve equal length, thereby meeting the time lag requirement.

The serpentine line should generally be placed at the source of the loss of length, not at the far end. Only at the source can the signals at the positive and negative ends of the differential line be transmitted synchronously most of the time.

The bend in the trace is one of the sources of loss of length. For the bend of the trace, the equal length should be close to the bend (<=15mm)

If two traces are bent and the distance between them is less than 15mm, the loss of length between the two will compensate each other at this time, so there is no need to do equal length processing at this time.

For different parts of high-speed differential signal lines, the lengths should be independent and equal. Vias, series coupling capacitors, and interface terminals are all high-speed differential signal lines divided into two parts, so pay special attention at this time.

must be the same length separately. Because a lot of EDA software only pays attention to whether the entire wiring is lost in DRC.

For interfaces such as LVDS display devices, there will be several pairs of differential pairs at the same time, and the timing requirements between the differential pairs are generally very strict, and the time delay requirements are particularly small. Therefore, for such differential signal pairs, we generally require them to be in the same plane. Make compensation. Because the signal transmission speed of different layers is different.

When some EDA software calculates the length of the trace, the trace inside the pad will also be calculated within the length. If the length compensation is performed at this time, the actual result will lose the length. So pay special attention at this time when using some EDA software.

At any time, if you can, you must choose a symmetrical outlet to avoid the need to eventually perform a serpentine routing for equal length.

If space permits, try to add a small loop at the source of the short differential line to achieve compensation instead of using a serpentine line to compensate.

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